UM10360 Datasheet, PDF (602/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller
Table 565. DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0)
Bit
Name
Function
0
E
Channel enable. Reading this bit indicates whether a channel is currently enabled or
disabled:
0 = channel disabled.
1 = channel enabled.
The Channel Enable bit status can also be found by reading the DMACEnbldChns
Register.
A channel is enabled by setting this bit.
A channel can be disabled by clearing the Enable bit. This causes the current AHB
transfer (if one is in progress) to complete and the channel is then disabled. Any data
in the FIFO of the relevant channel is lost. Restarting the channel by setting the
Channel Enable bit has unpredictable effects, the channel must be fully re-initialized.
The channel is also disabled, and Channel Enable bit cleared, when the last LLI is
reached, the DMA transfer is completed, or if a channel error is encountered.
If a channel must be disabled without losing data in the FIFO, the Halt bit must be set
so that further DMA requests are ignored. The Active bit must then be polled until it
reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable
bit can be cleared.
5:1
SrcPeripheral
Source peripheral. This value selects the DMA source request peripheral. This field is
ignored if the source of the transfer is from memory. See Table 31–544 for peripheral
identification.
10:6
DestPeripheral
Destination peripheral. This value selects the DMA destination request peripheral.
This field is ignored if the destination of the transfer is to memory. See Table 31–544
for peripheral identification.
13:11
TransferType
This value indicates the type of transfer. The transfer type can be
memory-to-memory, memory-to-peripheral, peripheral-to-memory, or
peripheral-to-peripheral.
Refer to Table 31–566 for the encoding of this field.
14
IE
Interrupt error mask. When cleared, this bit masks out the error interrupt of the
relevant channel.
15
ITC
Terminal count interrupt mask. When cleared, this bit masks out the terminal count
interrupt of the relevant channel.
16
L
Lock. When set, this bit enables locked transfers. This information is not used in the
LPC17xx.
17
A
Active:
0 = there is no data in the FIFO of the channel.
1 = the channel FIFO has data.
This value can be used with the Halt and Channel Enable bits to cleanly disable a
DMA channel. This is a read-only bit.
18
H
Halt:
0 = enable DMA requests.
1 = ignore further source DMA requests.
The contents of the channel FIFO are drained.
This value can be used with the Active and Channel Enable bits to cleanly disable a
DMA channel.
31:19
Reserved
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
602 of 835