UM10360 Datasheet, PDF (787/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
Table 685. RBAR bit assignments
[31:N]
ADDR
Region base address field. The value of N depends on the region size. For
more information see Section 34–4.5.4.1.
[(N-1):5] -
Reserved.
[4]
VALID MPU Region Number valid bit:
Write:
0 = RNR not changed, and the processor:
• updates the base address for the region specified in the RNR
• ignores the value of the REGION field
1 = the processor:
• updates the value of the RNR to the value of the REGION field
• updates the base address for the region specified in the REGION field.
Always reads as zero.
[3:0]
REGION MPU region field:
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the RNR.
4.5.4.1 The ADDR field
The ADDR field is bits[31:N] of the RBAR. The region size, as specified by the SIZE field
in the RASR, defines the value of N:
N = Log₂(Region size in bytes),
If the region size is configured to 4GB, in the RASR, there is no valid ADDR field. In this
case, the region occupies the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64KB region must
be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000.
4.5.5 MPU Region Attribute and Size Register
The RASR defines the region size and memory attributes of the MPU region specified by
the RNR, and enables that region and any subregions. See the register summary in
Table 34–681 for its attributes.
RASR is accessible using word or halfword accesses:
The bit assignments are shown in Table 34–686.
• the most significant halfword holds the region attributes
• the least significant halfword holds the region size and the region and subregion
enable bits.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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