UM10360 Datasheet, PDF (141/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 10: LPC17xx Ethernet
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision backoff and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
• Physical interface:
– Attachment of external PHY chip through a standard Reduced MII (RMII) interface.
– PHY register access is available via the Media Independent Interface Management
(MIIM) interface.
4. Architecture and operation
Figure 10–16 shows the internal architecture of the Ethernet block.
register
interface (AHB
slave)
HOST
REGISTERS
TRANSMIT
FLOW
CONTROL
TRANSMIT
DMA
TRANSMIT
RETRY
RMII
DMA interface
(AHB master)
ETHERNET
BLOCK
RECEIVE
DMA
RECEIVE
BUFFER
RECEIVE
FILTER
MIIM
Fig 16. Ethernet block diagram
The block diagram for the Ethernet block consists of:
• The host registers module containing the registers in the software view and handling
AHB accesses to the Ethernet block. The host registers connect to the transmit and
receive data path as well as the MAC.
• The DMA to AHB interface. This provides an AHB master connection that allows the
Ethernet block to access on-chip SRAM for reading of descriptors, writing of status,
and reading and writing data buffers.
• The Ethernet MAC, which interfaces to the off-chip PHY via an RMII interface.
• The transmit data path, including:
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
141 of 835