UM10360 Datasheet, PDF (809/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 35: LPC17xx Supplementary information
I2C1DATA_BUFFER- 0x4005 C02C; I²C2,
I2C2DATA_BUFFER- 0x400A 002C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .443
Table 391.I²C Slave Address registers (I2ADR0 to 3: I²C0,
I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, 20, 24, 28];
I²C1, I2C1ADR[0, 1, 2, 3] - address
0x4005 C0[0C, 20, 24, 28]; I²C2, I2C2ADR[0, 1, 2,
3] - address 0x400A 00[0C, 20, 24, 28]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .443
Table 392.I²C Mask registers (I2MASK0 to 3: I²C0,
I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, 38, 3C];
I²C1, I2C1MASK[0, 1, 2, 3] - address
0x4005 C0[30, 34, 38, 3C]; I²C2, I2C2MASK[0, 1,
2, 3] - address 0x400A 00[30, 34, 38, 3C]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .444
Table 393.I²C SCL HIGH Duty Cycle register (I2SCLH: I²C0,
I2C0SCLH - address 0x4001 C010; I²C1,
I2C1SCLH - address 0x4005 C010; I²C2,
I2C2SCLH - 0x400A 0010) bit description . . .444
Table 394.I²C SCL Low duty cycle register (I2SCLL: I²C0 -
I2C0SCLL: 0x4001 C014; I²C1 - I2C1SCLL:
0x4005 C014; I²C2 - I2C2SCLL: 0x400A 0014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .444
Table 395.Example I²C clock rates . . . . . . . . . . . . . . . . .445
Table 396.Abbreviations used to describe an I²C
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .446
Table 397.I2CONSET used to initialize Master Transmitter
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447
Table 398.I2CONSET used to initialize Slave Receiver
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451
Table 399.Master Transmitter mode . . . . . . . . . . . . . . . .454
Table 400.Master Receiver mode . . . . . . . . . . . . . . . . . .455
Table 401.Slave Receiver mode . . . . . . . . . . . . . . . . . . .456
Table 402.Slave Transmitter mode . . . . . . . . . . . . . . . . .458
Table 403.Miscellaneous States . . . . . . . . . . . . . . . . . . .459
Table 404.Pin descriptions . . . . . . . . . . . . . . . . . . . . . . .472
Table 405.I2S register map . . . . . . . . . . . . . . . . . . . . . . .473
Table 406:Digital Audio Output register (I2SDAO - address
0x400A 8000) bit description . . . . . . . . . . . . .473
Table 407:Digital Audio Input register (I2SDAI - address
0x400A 8004) bit description . . . . . . . . . . . . .474
Table 408:Transmit FIFO register (I2STXFIFO - address
0x400A 8008) bit description . . . . . . . . . . . . .474
Table 409:Receive FIFO register (I2RXFIFO - address
0x400A 800C) bit description . . . . . . . . . . . . .475
Table 410:Status Feedback register (I2SSTATE - address
0x400A 8010) bit description . . . . . . . . . . . . .475
Table 411: DMA Configuration register 1 (I2SDMA1 - address
0x400A 8014) bit description . . . . . . . . . . . . .475
Table 412:DMA Configuration register 2 (I2SDMA2 - address
0x400A 8018) bit description . . . . . . . . . . . . .476
Table 413:Interrupt Request Control register (I2SIRQ -
address 0x400A 801C) bit description . . . . . . 476
Table 414:Transmit Clock Rate register (I2TXRATE -
address 0x400A 8020) bit description . . . . . . 477
Table 415:Receive Clock Rate register (I2SRXRATE -
address 0x400A 8024) bit description . . . . . . 478
Table 416:Transmit Clock Rate register (I2TXBITRATE -
address 0x400A 8028) bit description . . . . . . 478
Table 417:Receive Clock Rate register (I2SRXBITRATE -
address 0x400A 802C) bit description . . . . . . 478
Table 418:Transmit Mode Control register (I2STXMODE -
0x400A 8030) bit description . . . . . . . . . . . . . 479
Table 419:Receive Mode Control register (I2SRXMODE -
0x400A 8034) bit description . . . . . . . . . . . . . 479
Table 420:I2S transmit modes . . . . . . . . . . . . . . . . . . . . 481
Table 421:I2S receive modes . . . . . . . . . . . . . . . . . . . . . 483
Table 422.Conditions for FIFO level comparison . . . . . . 485
Table 423.DMA and interrupt request generation. . . . . . 485
Table 424.Status feedback in the I2SSTATE register . . . 485
Table 425.Timer/Counter pin description . . . . . . . . . . . . 488
Table 426.TIMER/COUNTER0-3 register map. . . . . . . . 489
Table 427.Interrupt Register (T[0/1/2/3]IR - addresses
0x4000 4000, 0x4000 8000, 0x4009 0000,
0x4009 4000) bit description . . . . . . . . . . . . . 490
Table 428.Timer Control Register (TCR, TIMERn: TnTCR -
addresses 0x4000 4004, 0x4000 8004,
0x4009 0004, 0x4009 4004) bit description . . 491
Table 429.Count Control Register (T[0/1/2/3]CTCR -
addresses 0x4000 4070, 0x4000 8070,
0x4009 0070, 0x4009 4070) bit description . . 491
Table 430.Match Control Register (T[0/1/2/3]MCR -
addresses 0x4000 4014, 0x4000 8014,
0x4009 0014, 0x4009 4014) bit description . . 493
Table 431.Capture Control Register (T[0/1/2/3]CCR -
addresses 0x4000 4028, 0x4000 8020,
0x4009 0028, 0x4009 4028) bit description . . 494
Table 432.External Match Register (T[0/1/2/3]EMR -
addresses 0x4000 403C, 0x4000 803C,
0x4009 003C, 0x4009 403C) bit description . 495
Table 433.External Match Control . . . . . . . . . . . . . . . . . 495
Table 434.Repetitive Interrupt Timer register map . . . . . 498
Table 435.RI Compare Value register (RICOMPVAL -
address 0x400B 0000) bit description . . . . . . 498
Table 436.RI Compare Value register (RICOMPVAL -
address 0x400B 0004) bit description . . . . . . 498
Table 437.RI Control register (RICTRL - address 0x400B
0008) bit description. . . . . . . . . . . . . . . . . . . . 499
Table 438.RI Counter register (RICOUNTER - address
0x400B 000C) bit description. . . . . . . . . . . . . 499
Table 439.System Tick Timer register map. . . . . . . . . . . 502
Table 440.System Timer Control and status register
continued >>
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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