UM10360 Datasheet, PDF (494/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 21: LPC17xx Timer 0/1/2/3
6.9 Capture Registers (CR0 - CR1)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
6.10 Capture Control Register (T[0/1/2/3]CCR - 0x4000 4028, 0x4000 8028,
0x4009 0028, 0x4009 4028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, "n" represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
Table 431. Capture Control Register (T[0/1/2/3]CCR - addresses 0x4000 4028, 0x4000 8020, 0x4009 0028,
0x4009 4028) bit description
Bit Symbol Value Description
Reset
Value
0
CAP0RE 1
Capture on CAPn.0 rising edge: a sequence of 0 then 1 on CAPn.0 will cause CR0 to be 0
loaded with the contents of TC.
0
This feature is disabled.
1
CAP0FE 1
Capture on CAPn.0 falling edge: a sequence of 1 then 0 on CAPn.0 will cause CR0 to be 0
loaded with the contents of TC.
0
This feature is disabled.
2
CAP0I 1
Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event will generate an interrupt. 0
0
This feature is disabled.
3
CAP1RE 1
Capture on CAPn.1 rising edge: a sequence of 0 then 1 on CAPn.1 will cause CR1 to be 0
loaded with the contents of TC.
0
This feature is disabled.
4
CAP1FE 1
Capture on CAPn.1 falling edge: a sequence of 1 then 0 on CAPn.1 will cause CR1 to be 0
loaded with the contents of TC.
0
This feature is disabled.
5
CAP1I 1
Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event will generate an interrupt. 0
0
This feature is disabled.
31:6 -
Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.
6.11 External Match Register (T[0/1/2/3]EMR - 0x4000 403C, 0x4000 803C,
0x4009 003C, 0x4009 403C)
The External Match Register provides both control and status of the external match pins.
In the descriptions below, “n” represents the Timer number, 0 or 1, and “m” represent a
Match number, 0 through 3.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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