UM10360 Datasheet, PDF (121/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
Table 101. GPIO interrupt register map
Generic
Name
Description
IntEnR
GPIO Interrupt Enable for Rising edge.
IntEnF
GPIO Interrupt Enable for Falling edge.
IntStatR GPIO Interrupt Status for Rising edge.
IntStatF GPIO Interrupt Status for Falling edge.
IntClr
GPIO Interrupt Clear.
IntStatus GPIO overall Interrupt Status.
Access
R/W
R/W
RO
RO
WO
RO
Reset
value^[1]
0
0
0
0
0
0
PORTn Register
Name & Address
IO0IntEnR - 0x4002 8090
IO2IntEnR - 0x4002 80B0
IO0IntEnR - 0x4002 8094
IO2IntEnR - 0x4002 80B4
IO0IntStatR - 0x4002 8084
IO2IntStatR - 0x4002 80A4
IO0IntStatF - 0x4002 8088
IO2IntStatF - 0x4002 80A8
IO0IntClr - 0x4002 808C
IO2IntClr - 0x4002 80AC
IOIntStatus - 0x4002 8080
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
5.1 GPIO port Direction register FIOxDIR (FIO0DIR to FIO4DIR- 0x2009
C000 to 0x2009 C080)
This word accessible register is used to control the direction of the pins when they are
configured as GPIO port pins. Direction bit for any pin must be set according to the pin
functionality.
Note that GPIO pins P0.29 and P0.30 are shared with the USB_D+ and USB_D- pins and
must have the same direction. If either FIO0DIR bit 29 or 30 are configured as zero, both
P0.29 and P0.30 will be inputs. If both FIO0DIR bits 29 and 30 are ones, both P0.29 and
P0.30 will be outputs.
Table 102. Fast GPIO port Direction register FIO0DIR to FIO4DIR - addresses 0x2009 C000 to
0x2009 C080) bit description
Bit Symbol Value Description
Reset
value
31:0 FIO0DIR
Fast GPIO Direction PORTx control bits. Bit 0 in FIOxDIR
0x0
FIO1DIR
controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31.
FIO2DIR ₀
FIO3DIR
FIOI4DIR ¹
Controlled pin is input.
Controlled pin is output.
Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed in
Table 9–103, too. Next to providing the same functions as the FIODIR register, these
additional registers allow easier and faster access to the physical port pins.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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