UM10360 Datasheet, PDF (477/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 20: LPC17xx I2S interface
Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
greater than or equal to X.
Table 414: Transmit Clock Rate register (I2TXRATE - address 0x400A 8020) bit description
Bit Symbol Description
Reset
Value
7:0
Y_divider I²S transmit MCLK rate denominator. This value is used to divide PCLK to produce the
0
transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of
0 stops the clock.
15:8 X_divider I²S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the
0
transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide
range of possibilities. Note: the resulting ratio X/Y is divided by 2.
31:16 -
Reserved, user software should not write ones to reserved bits. The value read from a
NA
reserved bit is not defined.
5.9.1 Notes on fractional rate generators
The nature of a fractional rate generator is that there will be some output jitter with some
divide settings. This is because the fractional rate generator is a fully digital function, so
output clock transitions are synchronous with the source clock, whereas a theoretical
perfect fractional rate may have edges that are not related to the source clock. So, output
jitter will not be greater than plus or minus one source clock between consecutive clock
edges.
For example, if X = 0x07 and Y = 0x11, the fractional rate generator will output 7 clocks for
every 17 (11 hex) input clocks, distributed as evenly as it can. In this example, there is no
way to distribute the output clocks in a perfectly even fashion, so some clocks will be
longer than others. The output is divided by 2 in order to square it up, which also helps
with the jitter. The frequency averages out to exactly (7/17) / 2, but some clocks will be a
slightly different length than their neighbors. It is possible to avoid jitter entirely by
choosing fractions such that X divides evenly into Y, such as 2/4, 2/6, 3/9, 1/N, etc.
5.10 Receive Clock Rate register (I2SRXRATE - 0x400A 8024)
The MCLK rate for the I²S receiver is determined by the values in the I2SRXRATE
register. The required I2SRXRATE setting depends on the peripheral clock rate
(PCLK_I2S) and the desired MCLK rate (such as 256 fs).
The receiver MCLK rate is generated using a fractional rate generator, dividing down the
frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be
chosen to produce a frequency twice that desired for the receiver MCLK, which must be
an integer multiple of the receiver bit clock rate. Fractional rate generators have some
aspects that the user should be aware of when choosing settings. These are discussed in
Section 20–5.9.1. The equation for the fractional rate generator is:
I2SRXMCLK = PCLK_I2S * (X/Y) /2
Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
greater than or equal to X.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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