UM10360 Datasheet, PDF (492/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 21: LPC17xx Timer 0/1/2/3
Table 429. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070,
0x4009 4070) bit description
Bit Symbol Value Description
3:2 Count
When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for
Input
clocking.
Select _{00 CAPn.0 for TIMERn}
01 CAPn.1 for TIMERn
10 Reserved
11 Reserved
Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits
for that input in the Capture Control Register (TnCCR) must be programmed as 000.
However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the
same timer.
31:4 -
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Reset
Value
00
NA
6.4 Timer Counter registers (T0TC - T3TC, 0x4000 4008, 0x4000 8008,
0x4009 0008, 0x4009 4008)
The 32-bit Timer Counter register is incremented when the prescale counter reaches its
terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will
count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.
This event does not cause an interrupt, but a match register can be used to detect an
overflow if needed.
6.5 Prescale register (T0PR - T3PR, 0x4000 400C, 0x4000 800C,
0x4009 000C, 0x4009 400C)
The 32-bit Prescale register specifies the maximum value for the Prescale Counter.
6.6 Prescale Counter register (T0PC - T3PC, 0x4000 4010, 0x4000 8010,
0x4009 0010, 0x4009 4010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship of the resolution of the
timer versus the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale register,
the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK.
This causes the Timer Counter to increment on every PCLK when PR = 0, every 2 pclks
when PR = 1, etc.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
492 of 835