UM10360 Datasheet, PDF (584/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller
• Supports 8-bit, 16-bit, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
• DMA can operate in Sleep mode. (Note that in Sleep mode the GPDMA cannot
access the flash memory).
4. Functional description
This section describes the major functional blocks of the DMA Controller.
4.1 DMA controller functional description
The DMA Controller enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master. Figure 31–133 shows a block diagram of the
DMA Controller.
AHB BUS
AHB SLAVE
INTERFACE
DMA
requests
DMA
responses
DMA
Interrupts
DMA
REQUEST
AND
RESPONSE
INTERFACE
INTERRUPT
REQUEST
GPDMA
CONTROL
LOGIC AND
REGISTERS
CHANNEL
LOGIC AND
REGISTERS
AHB
MASTER
INTERFACE
AHB BUS
Fig 133. DMA controller block diagram
The functions of the DMA Controller are described in the following sections.
4.1.1 AHB slave interface
All transactions to DMA Controller registers on the AHB slave interface are 32 bits wide.
8-bit and 16-bit accesses are not supported and will result in an exception.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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