UM10360 Datasheet, PDF (64/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 4: LPC17xx Clocking and power control
Each bit in PCONP controls one peripheral as shown in Table 4–46.
If a peripheral control bit is 1, that peripheral is enabled. If a peripheral control bit is 0, that
peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the
I²C1 interface is enabled. If bit 19 is 0, the I²C1 interface is disabled.
Important: valid read from a peripheral register and valid write to a peripheral
register is possible only if that peripheral is enabled in the PCONP register!
Table 46. Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit
description
Bit Symbol
Description
Reset
value
0-
Reserved.
NA
1 PCTIM0 Timer/Counter 0 power/clock control bit.
1
2 PCTIM1 Timer/Counter 1 power/clock control bit.
1
3 PCUART0 UART0 power/clock control bit.
1
4 PCUART1 UART1 power/clock control bit.
1
5-
Reserved.
NA
6 PCPWM1 PWM1 power/clock control bit.
1
7 PCI2C0
The I²C0 interface power/clock control bit.
1
8 PCSPI
The SPI interface power/clock control bit.
1
9 PCRTC
The RTC power/clock control bit.
1
10 PCSSP1 The SSP 1 interface power/clock control bit.
1
11 -
Reserved.
NA
12 PCADC
A/D converter (ADC) power/clock control bit.
0
Note: Clear the PDN bit in the AD0CR before clearing this bit, and set
this bit before setting PDN.
13 PCCAN1 CAN Controller 1 power/clock control bit.
0
14 PCCAN2 CAN Controller 2 power/clock control bit.
0
15 -
Reserved.
NA
16 PCRIT
Repetitive Interrupt Timer power/clock control bit.
0
17 PCMCPWM Motor Control PWM
0
18 PCQEI
Quadrature Encoder Interface power/clock control bit.
0
19 PCI2C1
The I²C1 interface power/clock control bit.
1
20 -
Reserved.
NA
21 PCSSP0 The SSP0 interface power/clock control bit.
1
22 PCTIM2
Timer 2 power/clock control bit.
0
23 PCTIM3
Timer 3 power/clock control bit.
0
24 PCUART2 UART 2 power/clock control bit.
0
25 PCUART3 UART 3 power/clock control bit.
0
26 PCI2C2
I²C interface 2 power/clock control bit.
1
27 PCI2S
I²S interface power/clock control bit.
0
28 -
Reserved.
NA
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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