UM10360 Datasheet, PDF (184/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 10: LPC17xx Ethernet
• In the case of a transmission error (LateCollision, ExcessiveCollision, or
ExcessiveDefer) or a multi-fragment frame where the device driver did provide the
initial fragments but did not provide the rest of the fragments (NoDescriptor) or in the
case of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus
register.
All of the above interrupts can be enabled and disabled by setting or resetting the
corresponding bits in the IntEnable register. Enabling or disabling does not affect the
IntStatus register contents, only the propagation of the interrupt status to the CPU (via the
NVIC).
The interrupts, either of individual frames or of the whole list, are a good means of
communication between the DMA manager and the device driver, triggering the device
driver to inspect the status words of descriptors that have been processed.
Transmit example
Figure 10–20 illustrates the transmit process in an example transmitting uses a frame
header of 8 bytes and a frame payload of 12 bytes.
TxDescriptor
0x200810EC
TxStatus
0x200811F8
0x200810EC
Packet
0x20081314
0x200810F0
0 0 COonNtrToRl OL 7
0x200810F4
Packet
0x20081411
0x200810F8 _{0 0 CCOonNtrToRl OL 7}
0x200810FC
Packet
0x20081419
PACKET 0 HEADER (8 bytes)
PACKET 0 PAYLOAD (12 bytes)
0x200811F8
StatusInfo
0x200811FC
StatusInfo
StatusInfo ^0x20081200
StatusInfo ^0x20081204
0x20081100 1 1 CCOonNtrToRl OL 3
0x20081104
Packet
0x20081324
0x20081108 ^{0 0 CCOonNtrToRl OL 7}
descriptor array
PACKET 1 HEADER (8 bytes)
TxProduceIndex
TxConsumeIndex
TxDescriptorNumber
=3
fragment buffers
status array
Fig 20. Transmit example memory and registers
UM10360_1
User manual
After reset the values of the DMA registers will be zero. During initialization the device
driver will allocate the descriptor and status array in memory. In this example, an array of
four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
184 of 835