UM10360 Datasheet, PDF (745/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
3.3.4 Vector table
The vector table contains the reset value of the stack pointer, and the start addresses,
also called exception vectors, for all exception handlers. Figure 34–146 shows the order
of the exception vectors in the vector table. The least-significant bit of each vector must be
1, indicating that the exception handler is Thumb code. Note that the upper limit of the IRQ
number is device dependent.
Exception
number
127
.
.
.
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
IRQ
number
111
2
1
0
-1
-2
-5
-10
-11
-12
-13
-14
Offset
0x1FC
.
.
.
0x004C
0x0048
0x0044
0x0040
0x003C
0x0038
0x002C
Vector
IRQ111
.
.
.
IRQ2
IRQ1
IRQ0
Systick
PendSV
Reserved
Reserved for debug
SVCall
Reserved
0x0018
Usage fault
0x0014
Bus fault
0x0010 Memory management fault
0x000C
Hard fault
0x0008
NMI
0x0004
Reset
0x0000
Initial SP value.
Fig 146. Vector table
On system reset, the vector table is fixed at address 0x00000000. Privileged software can
write to the VTOR to relocate the vector table start address to a different memory location,
in the range 0x00000080 to 0x3FFFFF80, see Section 34–4.3.5 “Vector Table Offset Register”.
3.3.5 Exception priorities
As Table 34–640 shows, all exceptions have an associated priority, with:
• a lower priority value indicating a higher priority
• configurable priorities for all exceptions except Reset, Hard fault, and NMI.
If software does not configure any priorities, then all exceptions with a configurable priority
have a priority of 0. For information about configuring exception priorities see
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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