UM10360 Datasheet, PDF (758/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority
Registers. For more information see the description of the NVIC_SetPriority function in
Section 34–4.2.10.1 “NVIC programming hints”. Table 34–646 shows how the interrupts,
or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables that
have one bit per interrupt.
Table 646. Mapping of interrupts to the interrupt variables
Interrupts CMSIS array elements^[1]
Set-enable Clear-enable Set-pending
0-31
ISER[0]
ICER[0]
ISPR[0]
32-63
ISER[1]
ICER[1]
ISPR[1]
64-95
ISER[2]
ICER[2]
ISPR[2]
96-127
ISER[3]
ICER[3]
ISPR[3]
Clear-pending
ICPR[0]
ICPR[1]
ICPR[2]
ICPR[3]
Active Bit
IABR[0]
IABR[1]
IABR[2]
IABR[3]
[1] Each array element corresponds to a single NVIC register, for example the element ICER[1] corresponds to the ICER1 register.
4.2.2 Interrupt Set-enable Registers
The ISER0-ISER3 registers enable interrupts, and show which interrupts are enabled.
See:
• the register summary in Table 34–645 for the register attributes
• Table 34–646 for which interrupts are controlled by each register.
The bit assignments are shown in Table 34–647.
Table 647. ISER bit assignments
Bits
Name
Function
[31:0]
SETENA
Interrupt set-enable bits.
Write:
0 = no effect
1 = enable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to
pending, but the NVIC never activates the interrupt, regardless of its priority.
4.2.3 Interrupt Clear-enable Registers
The ICER0-ICER3 registers disable interrupts, and show which interrupts are enabled.
See:
• the register summary in Table 34–645 for the register attributes
• Table 34–646 for which interrupts are controlled by each register.
The bit assignments are shown in Table 34–648.
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
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