UM10360 Datasheet, PDF (552/835 Pages) NXP Semiconductors – LPC17xx User manual

NXP Semiconductors
UM10360
Chapter 26: LPC17xx Quadrature Encoder Interface (QEI)
Table 502: QEI Interrupt Set register (QEISET - address 0x400B CFEC) bit description
Bit Symbol
Description
Reset
value
10
POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set 0
and the REV_Int is set.
11
POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set 0
and the REV_Int is set.
12
POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set 0
and the REV_Int is set.
31:13 -
reserved
0
6.4.3 QEI Interrupt Clear register (QEICLR - 0x400B CFE8)
Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Status
register (QEISTAT).
Table 503: QEI Interrupt Clear register (QEICLR - 0x400B CFE8) bit description
Bit Symbol
Description
0
1
2
3
4
5
6
7
8
9
10
11
12
31:13
INX_Int
Indicates that an index pulse was detected.
TIM_Int
Indicates that a velocity timer overflow occurred
VELC_Int
Indicates that captured velocity is less than compare velocity.
DIR_Int
Indicates that a change of direction was detected.
ERR_Int
Indicates that an encoder phase error was detected.
ENCLK_Int Indicates that and encoder clock pulse was detected.
POS0_Int
Indicates that the position 0 compare value is equal to the current position.
POS1_Int
Indicates that the position 1compare value is equal to the current position.
POS2_Int
Indicates that the position 2 compare value is equal to the current position.
REV_Int
Indicates that the index compare value is equal to the current index count.
POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set
and the REV_Int is set.
POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set
and the REV_Int is set.
POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set
and the REV_Int is set.
-
reserved
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
6.4.4 QEI Interrupt Enable register (QEIIE - 0x400B CFE4)
This register enables interrupt sources. Bits set to 1 enable the corresponding interrupt; a
0 bit disables the corresponding interrupt.
Table 504: QEI Interrupt Enable register (QEIIE - address 0x400B CFE4) bit description
Bit Symbol
Description
0
INX_Int
Indicates that an index pulse was detected.
1
TIM_Int
Indicates that a velocity timer overflow occurred
2
VELC_Int
Indicates that captured velocity is less than compare velocity.
3
DIR_Int
Indicates that a change of direction was detected.
Reset
value
0
0
0
0
UM10360_1
User manual
Rev. 01 — 4 January 2010
© NXP B.V. 2010. All rights reserved.
552 of 835