MC68HC908JL3E Datasheet, PDF (99/226 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
SIM Registers
Address: $FE01
Bit 7
6
5
4
3
2
1
Bit 0
Read: POR
PIN
COP ILOP ILAD MODRST LVI
0
Write:
POR: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-21. Reset Status Register (RSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset bit
1 = Last reset caused by monitor mode entry when vector locations
$FFFE and $FFFF are $FF after POR while IRQ1 = V_DD
0 = POR or read of SRSR
LVI — Low Voltage Inhibit Reset bit
1 = Last reset caused by LVI circuit
0 = POR or read of SRSR
MC68H(R)C908JL3E/JK3E/JK1E — Rev. 2.0
MOTOROLA
System Integration Module (SIM)
Technical Data
99