MC68HC908JL3E Datasheet, PDF (89/226 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
Exception Control
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 7-9 shows interrupt entry timing.
Figure 7-10 shows interrupt recovery timing.
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4 VECT H VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
Figure 7-9. Interrupt Entry
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
CCR
A
X PC – 1[15:8] PC – 1[7:0] OPCODE OPERAND
Figure 7-10. Interrupt Recovery
7.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
MC68H(R)C908JL3E/JK3E/JK1E — Rev. 2.0
MOTOROLA
System Integration Module (SIM)
Technical Data
89