MC68HC908JL3E Datasheet, PDF (175/226 Pages) Motorola, Inc – Microcontrollers

Keyboard Interrupt Module (KBI)
Functional Description
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRA bits in the data direction register A.
2. Write logic 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
14.4.2 Keyboard Status and Control Register
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
Address: $001A
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
KEYF
0
IMASKK MODEK
Write:
ACKK
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0’s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port-
A. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
MC68H(R)C908JL3E/JK3E/JK1E — Rev. 2.0
MOTOROLA
Keyboard Interrupt Module (KBI)
Technical Data
175