MC68HC908JL3E Datasheet, PDF (81/226 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
SIM Bus Clock Control and Generation
7.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 7-3.
From
OSCILLATOR
From
OSCILLATOR
2OSCOUT
OSCOUT
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 7-3. SIM Clock Signals
7.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
(2OSCOUT) divided by four.
7.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 2OSCOUT cycle POR time-out has completed. The RST pin is
driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the time-out.
7.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
2OSCOUT to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay time-out. This time-out is
selectable as 4096 or 32 2OSCOUT cycles. (See 7.7.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
MC68H(R)C908JL3E/JK3E/JK1E — Rev. 2.0
MOTOROLA
System Integration Module (SIM)
Technical Data
81