MC68HC908JL3E Datasheet, PDF (65/226 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
CPU During Break Interrupts
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
6.9 Opcode Map
The opcode map is provided in Table 6-2.
MC68H(R)C908JL3E/JK3E/JK1E — Rev. 2.0
MOTOROLA
Central Processor Unit (CPU)
Technical Data
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