MC68HC908JL3E Datasheet, PDF (110/226 Pages) Motorola, Inc – Microcontrollers

Monitor ROM (MON)
9.4.1 Entering Monitor Mode
Table 9-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If IRQ1 = V_DD + V_HI:
– Clock on OSC1 is 4.9125MHz (EXT OSC or XTAL)
– PTB3 = low
2. If IRQ1 = V_DD + V_HI:
– Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL)
– PTB3 = high
3. If $FFFE & $FFFF is blank (contains $FF):
– Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL or RC)
– IRQ1 = V_DD
Table 9-1. Monitor Mode Entry Requirements and Options
OSC1 Frequency
Bus
Frequency
Comments
V_DD + V_HI⁽²⁾
X
0011
4.9152 MHz
2.4576MHz _{High-voltage entry to}
(OSC1 ÷ 2) _{monitor mode.}⁽³⁾
V_DD + V_HI
X
1011
9.8304 MHz
2.4576MHz ^{9600 baud communication}
(OSC1 ÷ 4) ^{on PTB0. COP disabled.}
V_DD
BLANK
(contain X X X 1
$FF)
9.8304 MHz
2.4576 MHz
(OSC1 ÷ 4)
Low-voltage entry to
monitor mode.⁽⁴⁾
9600 baud communication
on PTB0. COP disabled.
V_DD
NOT
BLANK
XXXX
At desired
frequency
OSC1 ÷ 4 Enters User mode.
Notes:
1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM when using V_DD + V_HI for monitor mode entry.
The OSC1 clock must be 50% duty cycle for this condition.
2. See Table 18-4 for V_DD + V_HI voltage level requirements.
3. For IRQ1 = V_DD + V_HI:
MC68HRC908JL3E/JK3E/JK1E — clock must be EXT OSC.
MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.
4. For IRQ1 = V_DD:
MC68HRC908JL3E/JK3E/JK1E — clock must be RC OSC.
MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.
Technical Data
110
MC68H(R)C908JL3E/JK3E/JK1E — Rev. 2.0
Monitor ROM (MON)
MOTOROLA