MC68HC908JL3E Datasheet, PDF (134/226 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
10.10.1 TIM Status and Control Register (TSC)
The TIM status and control register does the following:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: $0020
Bit 7
6
5
4
3
2
1
Bit 0
Read: TOF
0
0
TOIE TSTOP
Write: 0
TRST
PS2
PS1
PS0
Reset: 0
0
1
0
0
0
0
0
= Unimplemented
Figure 10-4. TIM Status and Control Register (TSC)
Technical Data
134
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo
value programmed in the TIM counter modulo registers. Clear TOF by
reading the TIM status and control register when TOF is set and then
writing a logic zero to TOF. If another TIM overflow occurs before the
clearing sequence is complete, then writing logic zero to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic
one to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
MC68H(R)C908JL3E/JK3E/JK1E — Rev. 2.0
Timer Interface Module (TIM)
MOTOROLA