MC68HC908JL3E Datasheet, PDF (140/226 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output
level of the TCHx pin. (See Table 10-3.) Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to an I/O port, and pin TCHx is available as a general-purpose I/O pin.
Table 10-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 10-3. Mode, Edge, and Level Selection
MSxB
X
X
0
0
0
0
0
0
1
1
1
MSxA
0
1
0
0
0
1
1
1
X
X
X
ELSxB
0
0
0
1
1
0
1
1
0
1
1
ELSxA Mode
Configuration
0
Output
Pin under Port Control;
Initial Output Level High
0
Preset
Pin under Port Control;
Initial Output Level Low
1
Capture on Rising Edge Only
0
Input
Capture
Capture on Falling Edge Only
1
Capture on Rising or Falling Edge
1
Toggle Output on Compare
Output
0
Compare Clear Output on Compare
or PWM
1
Set Output on Compare
1
Buffered Toggle Output on Compare
Output
0
Compare or ^{Clear Output on Compare}
Buffered
1
PWM ^{Set Output on Compare}
Technical Data
140
MC68H(R)C908JL3E/JK3E/JK1E — Rev. 2.0
Timer Interface Module (TIM)
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