MC68HC908JL3E Datasheet, PDF (136/226 Pages) Motorola, Inc – Microcontrollers

Timer Interface Module (TIM)
10.10.2 TIM Counter Registers (TCNTH:TCNTL)
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: $0021 TCNTH
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10
Bit9
Bit8
Write:
Reset: 0
0
0
0
0
0
0
0
Address: $0022 TCNTL
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-5. TIM Counter Registers (TCNTH:TCNTL)
Technical Data
136
MC68H(R)C908JL3E/JK3E/JK1E — Rev. 2.0
Timer Interface Module (TIM)
MOTOROLA