PIC18F2450 Datasheet, PDF (96/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
8.5 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1 and IPR2). Using the
priority bits requires that the Interrupt Priority Enable
(IPEN) bit be set.
REGISTER 8-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0
—
bit 7
R/W-1
R/W-1
R/W-1
U-0
R/W-1
R/W-1
ADIP
RCIP
TXIP
—
CCP1IP
TMR2IP
R/W-1
TMR1IP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
DS39760A-page 94
Advance Information
© 2006 Microchip Technology Inc.