PIC18F2450 Datasheet, PDF (203/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
18.2 Watchdog Timer (WDT)
For PIC18F2450/4450 devices, the WDT is driven by
the INTRC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed or a clock failure has occurred.
.
FIGURE 18-1:
WDT BLOCK DIAGRAM
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
18.2.1 CONTROL REGISTER
Register 18-15 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
SWDTEN
WDTEN
INTRC Source
CLRWDT
All Device Resets
WDTPS<3:0>
SLEEP
Enable WDT
INTRC Control
WDT Counter
÷128
Programmable Postscaler ^Reset
1:1 to 1:32,768
WDT
4
Wake-up from
Power-Managed
Modes
WDT
Reset
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 201