PIC18F2450 Datasheet, PDF (192/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
18.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction, with the TBLPTR pointing to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
TABLE 18-1: CONFIGURATION BITS AND DEVICE IDs
File Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
300000h CONFIG1L —
— USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 --00 0000
300001h CONFIG1H IESO FCMEN —
—
FOSC3 FOSC2 FOSC1 FOSC0 00-- 0101
300002h CONFIG2L —
— VREGEN BORV1 BORV0 BOREN1 BOREN0 PWRTEN --01 1111
300003h CONFIG2H —
—
— WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE —
—
—
300006h CONFIG4L DEBUG XINST ICPRT⁽²⁾
—
— LPT1OSC PBADEN
—
BBSIZ
LVP
—
STVREN
1--- -01-
100- 01-1
300008h CONFIG5L —
—
—
—
—
—
CP1
CP0
---- --11
300009h CONFIG5H —
CPB
—
—
—
—
—
—
-1-- ----
30000Ah CONFIG6L —
—
—
—
—
—
WRT1 WRT0 ---- --11
30000Bh CONFIG6H —
WRTB WRTC
—
—
—
—
—
-11- ----
30000Ch CONFIG7L —
—
—
—
—
—
EBTR1 EBTR0 ---- --11
30000Dh CONFIG7H
3FFFFEh DEVID1
3FFFFFh DEVID2
—
DEV2
DEV10
EBTRB
DEV1
DEV9
—
DEV0
DEV8
—
REV4
DEV7
—
REV3
DEV6
—
REV2
DEV5
—
REV1
DEV4
—
REV0
DEV3
-1-- ----
xxxx xxxx⁽¹⁾
0001 0010⁽¹⁾
Legend:
Note 1:
2:
x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
See Register 18-13 and Register 18-14 for device ID values. DEVID registers are read-only and cannot be programmed
by the user.
Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.
DS39760A-page 190
Advance Information
© 2006 Microchip Technology Inc.