PIC18F2450 Datasheet, PDF (294/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
TABLE 21-18: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
PIC18FXXXX
PIC18LFXXXX
0.7 25.0⁽¹⁾ μs TOSC based, VREF ≥ 3.0V
1.4 25.0⁽¹⁾ μs VDD = 2.0V,
TOSC based, VREF full range
PIC18FXXXX
TBD
1
μs A/D RC mode
PIC18LFXXXX
TBD
3
μs VDD = 2.0V,
A/D RC mode
131 TCNV Conversion Time
(not including acquisition time)⁽²⁾
132 TACQ Acquisition Time⁽³⁾
11
12
TAD
1.4
—
TBD
—
μs -40°C to +85°C
μs 0°C ≤ to ≤ +85°C
135 TSWC Switching Time from Convert → Sample
— (Note 4)
137 TDIS Discharge Time
0.2
—
μs
Legend:
Note 1:
2:
3:
4:
TBD = To Be Determined
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
On the following cycle of the device clock.
DS39760A-page 292
Advance Information
© 2006 Microchip Technology Inc.