PIC18F2450 Datasheet, PDF (145/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
14.5 USB Interrupts
The USB module can generate multiple interrupt
conditions. To accommodate all of these interrupt
sources, the module is provided with its own interrupt
logic structure, similar to that of the microcontroller.
USB interrupts are enabled with one set of control
registers and trapped with a separate set of flag regis-
ters. All sources are funneled into a single USB inter-
rupt request, USBIF (PIR2<5>), in the
microcontroller’s interrupt logic.
Figure 14-8 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction. Figure 14-9 shows some common events
within a USB frame and their corresponding interrupts.
FIGURE 14-8:
USB INTERRUPT LOGIC FUNNEL
Second Level USB Interrupts
(USB Error Conditions)
UEIR (Flag) and UEIE (Enable) Registers
Top Level USB Interrupts
(USB Status Interrupts)
UIR (Flag) and UIE (Enable) Registers
BTSEF
BTSEE
BTOEF
BTOEE
DFN8EF
DFN8EE
CRC16EF
CRC16EE
CRC5EF
CRC5EE
PIDEF
PIDEE
SOFIF
SOFIE
TRNIF
TRNIE
IDLEIF
IDLEIE
UERRIF
UERRIE
STALLIF
STALLIE
ACTVIF
ACTVIE
USBIF
URSTIF
URSTIE
FIGURE 14-9:
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
From Host From Host
SETUPToken Data
To Host
ACK
USB Reset
URSTIF
START-OF-FRAME
SOFIF
From Host
IN Token
To Host
Data
From Host
ACK
From Host From Host
OUT Token Empty Data
Transaction
To Host
ACK
Set TRNIF
Set TRNIF
Set TRNIF
Transaction
Complete
RESET
Differential Data
SOF
SETUP DATA STATUS
Control Transfer⁽¹⁾
SOF
1 ms Frame
Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 143