PIC18F2450 Datasheet, PDF (239/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Move Literal to W
MOVLW k
0 ≤ k ≤ 255
k→W
None
0000 1110 kkkk kkkk
The eight-bit literal ‘k’ is loaded into W.
1
1
Q2
Read
literal ‘k’
Q3
Process
Data
Q4
Write to W
Example:
MOVLW
5Ah
After Instruction
W
= 5Ah
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Move W to f
MOVWF f {,a}
0 ≤ f ≤ 255
a ∈ [0,1]
(W) → f
None
0110 111a ffff ffff
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
MOVWF
Before Instruction
W
= 4Fh
REG = FFh
After Instruction
W
REG
= 4Fh
= 4Fh
REG, 0
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 237