PIC18F2450 Datasheet, PDF (257/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
CALLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No
operation
Subroutine Call Using WREG
CALLW
None
(PC + 2) → TOS,
(W) → PCL,
(PCLATH) → PCH,
(PCLATU) → PCU
None
0000 0000 0001 0100
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Unlike CALL, there is no option to
update W, STATUS or BSR.
1
2
Q2
Read
WREG
No
operation
Q3
Push PC to
stack
No
operation
Q4
No
operation
No
operation
Example:
HERE
CALLW
Before Instruction
PC
=
PCLATH =
PCLATU =
W
=
After Instruction
PC
=
TOS =
PCLATH =
PCLATU =
W
=
address (HERE)
10h
00h
06h
001006h
address (HERE + 2)
10h
00h
06h
MOVSF
Move Indexed to f
Syntax:
Operands:
Operation:
Status Affected:
MOVSF [z_s], f_d
0 ≤ z_s ≤ 127
0 ≤ f_d ≤ 4095
((FSR2) + z_s) → f_d
None
Encoding:
1st word (source)
2nd word (destin.)
Description:
1110
1111
1011
ffff
0zzz zzzz_s
ffff ffff_d
The contents of the source register are
moved to destination register ‘f_d’. The
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z_s’ in the first word to the value of
FSR2. The address of the destination
register is specified by the 12-bit literal
‘f_d’ in the second word. Both addresses
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Decode
Decode
Q2
Q3
Determine Determine
source addr source addr
No
operation
No
operation
No dummy
read
Q4
Read
source reg
Write
register ‘f’
(dest)
Example:
MOVSF [05h], REG2
Before Instruction
FSR2
Contents
of 85h
REG2
= 80h
= 33h
= 11h
After Instruction
FSR2
Contents
of 85h
REG2
= 80h
= 33h
= 33h
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 255