PIC18F2450 Datasheet, PDF (144/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
TABLE 14-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
BDs Assigned to Endpoint
Endpoint
Mode 0
(No Ping-Pong)
Mode 1
(Ping-Pong on EP0 OUT)
Mode 2
(Ping-Pong on all EPs)
Out
In
Out
In
Out
In
0
0
1
0 (E), 1 (O)
2
1
2
3
3
4
2
4
5
5
6
3
6
7
7
8
4
8
9
9
10
5
10
11
11
12
6
12
13
13
14
7
14
15
15
16
8
16
17
17
18
9
18
19
19
20
10
20
21
21
22
11
22
23
23
24
12
24
25
25
26
13
26
27
27
28
14
28
29
29
30
15
30
31
31
32
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer
0 (E), 1 (O)
4 (E), 5 (O)
8 (E), 9 (O)
12 (E), 13 (O)
16 (E), 17 (O)
20 (E), 21 (O)
24 (E), 25 (O)
28 (E), 29 (O)
32 (E), 33 (O)
36 (E), 37 (O)
40 (E), 41 (O)
44 (E), 45 (O)
48 (E), 49 (O)
52 (E), 53 (O)
56 (E), 57 (O)
60 (E), 61 (O)
2 (E), 3 (O)
6 (E), 7 (O)
10 (E), 11 (O)
14 (E), 15 (O)
18 (E), 19 (O)
22 (E), 23 (O)
26 (E), 27 (O)
30 (E), 31 (O)
34 (E), 35 (O)
38 (E), 39 (O)
42 (E), 43 (O)
46 (E), 47 (O)
50 (E), 51 (O)
54 (E), 55 (O)
58 (E), 59 (O)
62 (E), 63 (O)
TABLE 14-5: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BDnSTAT⁽¹⁾
UOWN
DTS⁽⁴⁾
BDnCNT⁽¹⁾
BDnADRL⁽¹⁾
BDnADRH⁽¹⁾
Byte Count
Buffer Address Low
Buffer Address High
PID3⁽²⁾
PID2⁽²⁾
PID1⁽²⁾
PID0⁽²⁾
DTSEN⁽³⁾ BSTALL⁽³⁾
BC9
BC8
Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
2: Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 3 and 2 of the BDnSTAT
register are used to configure the DTSEN and BSTALL settings.
4: This bit is ignored unless DTSEN = 1.
DS39760A-page 142
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© 2006 Microchip Technology Inc.