PIC18F2450 Datasheet, PDF (212/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
Even when the dedicated port is enabled, the ICSP and
ICD functions remain available through the legacy port.
When VIH is seen on the MCLR/VPP/RE3 pin, the state
of the ICRST/ICVPP pin is ignored.
Note 1: The ICPRT Configuration bit can only be
programmed through the default ICSP
port.
2: The ICPRT Configuration bit must be
maintained clear for all 28-pin and 40-pin
devices; otherwise, unexpected operation
may occur.
18.9.2 28-PIN EMULATION
PIC18F4450 devices in 44-pin TQFP packages also
have the ability to change their configuration under
external control for debugging purposes. This allows
the device to behave as if it were a PIC18F2455/2550
28-pin device.
This 28-pin Configuration mode is controlled through a
single pin, NC/ICPORTS. Connecting this pin to VSS
forces the device to function as a 28-pin device.
Features normally associated with the 40/44-pin
devices are disabled, along with their corresponding
control registers and bits. On the other hand,
connecting the pin to VDD forces the device to function
in its default configuration.
The configuration option is only available when
background debugging and the dedicated ICD/ICSP
port are both enabled (DEBUG Configuration bit is
clear and ICPRT Configuration bit is set). When
disabled, NC/ICPORTS is a No Connect pin.
18.10 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply
ICSP Programming (formerly known as Low-Voltage
ICSP Programming or LVP). When Single-Supply
Programming is enabled, the microcontroller can be
programmed without requiring high voltage being
applied to the MCLR/VPP/RE3 pin, but the RB5/KBI1/
PGM pin is then dedicated to controlling Program
mode entry and is not available as a general purpose
I/O pin.
While programming using Single-Supply Program-
ming, VDD is applied to the MCLR/VPP/RE3 pin as in
normal execution mode. To enter Programming mode,
VDD is applied to the PGM pin.
Note 1: High-Voltage Programming is always
available, regardless of the state of the
LVP bit, by applying VIHH to the MCLR pin.
2: While in Low-Voltage ICSP Programming
mode, the RB5 pin can no longer be used
as a general purpose I/O pin and should
be held low during normal operation.
3: When using Low-Voltage ICSP Program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
4: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
(CONFIG4L<2> = 0); or
b) make certain that RB5/KBI1/PGM
is held low during entry into ICSP.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP/RE3 pin). Once LVP has been disabled, only the
standard high-voltage programming is available and
must be used to program the device.
Memory that is not code-protected can be erased using
either a Block Erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
erased, a Block Erase is required. If a Block Erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with VDD of 4.5V to 5.5V.
DS39760A-page 210
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© 2006 Microchip Technology Inc.