PIC18F2450 Datasheet, PDF (315/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

Timer0 .............................................................................. 111
16-Bit Mode Timer Reads and Writes ...................... 112
Associated Registers ............................................... 113
Clock Source Edge Select (T0SE Bit) ...................... 112
Clock Source Select (T0CS Bit) ............................... 112
Operation ................................................................. 112
Overflow Interrupt .................................................... 113
Prescaler .................................................................. 113
Switching Assignment ...................................... 113
Prescaler. See Prescaler, Timer0.
Timer1 .............................................................................. 115
16-Bit Read/Write Mode ........................................... 117
Associated Registers ....................................... 119, 126
Interrupt .................................................................... 118
Operation ................................................................. 116
Oscillator .......................................................... 115, 117
Layout Considerations ..................................... 118
Low-Power Option ........................................... 117
Using Timer1 as a Clock Source ..................... 117
Overflow Interrupt .................................................... 115
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 118
TMR1H Register ...................................................... 115
TMR1L Register ....................................................... 115
Use as a Real-Time Clock ....................................... 118
Timer2 .............................................................................. 121
Associated Registers ............................................... 122
Interrupt .................................................................... 122
Operation ................................................................. 121
Output ...................................................................... 122
PR2 Register ............................................................ 127
TMR2 to PR2 Match Interrupt .................................. 127
Timing Diagrams
A/D Conversion ........................................................ 291
Asynchronous Reception ......................................... 165
Asynchronous Transmission .................................... 163
Asynchronous Transmission
(Back to Back) ................................................. 163
Automatic Baud Rate Calculation ............................ 161
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 166
Auto-Wake-up Bit (WUE) During Sleep ................... 166
BRG Overflow Sequence ......................................... 161
Brown-out Reset (BOR) ........................................... 286
Capture/Compare/PWM (CCP) ................................ 288
CLKO and I/O .......................................................... 284
Clock/Instruction Cycle .............................................. 57
EUSART Synchronous Receive
(Master/Slave) ................................................. 289
EUSART Synchronous Transmission
(Master/Slave) ................................................. 289
External Clock (All Modes Except PLL) ................... 283
Fail-Safe Clock Monitor ............................................ 205
High/Low-Voltage Detect Characteristics ................ 280
High-Voltage Detect (VDIRMAG = 1) ...................... 186
Low-Voltage Detect (VDIRMAG = 0) ....................... 185
PWM Output ............................................................ 127
Reset, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and Power-up
Timer (PWRT) .................................................. 285
PIC18F2450/4450
Send Break Character Sequence ............................ 167
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 47
Synchronous Reception
(Master Mode, SREN) ..................................... 170
Synchronous Transmission ..................................... 168
Synchronous Transmission (Through TXEN) .......... 169
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) .......................................... 47
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ...................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ...................... 46
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 46
Timer0 and Timer1 External Clock .......................... 287
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 34
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 203
Transition for Wake from Idle to
Run Mode .......................................................... 38
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 36
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 35
Transition to RC_RUN Mode ..................................... 36
USB Signal .............................................................. 290
Timing Diagrams and Specifications ............................... 283
Capture/Compare/PWM
Requirements (CCP) ....................................... 288
CLKO and I/O Requirements ................................... 285
EUSART Synchronous Receive
Requirements .................................................. 289
EUSART Synchronous Transmission
Requirements .................................................. 289
External Clock Requirements .................................. 283
PLL Clock ................................................................ 284
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 286
Timer0 and Timer1 External Clock
Requirements .................................................. 287
USB Full-Speed Requirements ............................... 290
USB Low-Speed Requirements ............................... 290
Top-of-Stack Access .......................................................... 54
TQFP Packages and Special Features ........................... 209
TSTFSZ ........................................................................... 251
Two-Speed Start-up ................................................. 189, 203
Two-Word Instructions
Example Cases ......................................................... 58
TXSTA Register
BRGH Bit ................................................................. 157
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 313