PIC18F2450 Datasheet, PDF (287/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
TABLE 21-9: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max Units Conditions
10 TosH2ckL OSC1 ↑ to CLKO ↓
—
75
200
ns (Note 1)
11
TosH2ckH OSC1 ↑ to CLKO ↑
—
75
200
ns (Note 1)
12 TckR
CLKO Rise Time
—
35
100
ns (Note 1)
13 TckF
CLKO Fall Time
—
35
100
ns (Note 1)
14 TckL2ioV CLKO ↓ to Port Out Valid
—
— 0.5 TCY + 20 ns (Note 1)
15 TioV2ckH Port In Valid before CLKO ↑
0.25 TCY + 25 —
—
ns (Note 1)
16 TckH2ioI Port In Hold after CLKO ↑
0
—
—
ns (Note 1)
17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
50
150
ns
18 TosH2ioI OSC1 ↑ (Q2 cycle) to PIC18FXXXX
100
—
—
ns
18A
Port Input Invalid
PIC18LFXXXX
200
—
—
ns VDD = 2.0V
(I/O in hold time)
19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time)
0
—
—
ns
20 TioR
Port Output Rise Time PIC18FXXXX
—
10
25
ns
20A
PIC18LFXXXX
—
—
60
ns VDD = 2.0V
21 TioF
Port Output Fall Time PIC18FXXXX
—
10
25
ns
21A
PIC18LFXXXX
—
—
60
ns VDD = 2.0V
22† TINP
INT Pin High or Low Time
TCY
—
—
ns
23† TRBP
RB7:RB4 Change INT High or Low Time
TCY
—
—
ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
FIGURE 21-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
I/O pins
Note: Refer to Figure 21-4 for load conditions.
30
31
34
34
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 285