PIC18F2450 Datasheet, PDF (151/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
TABLE 14-6: REGISTERS ASSOCIATED WITH USB MODULE OPERATION⁽¹⁾
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details on
page
INTCON
IPR2
PIR2
PIE2
UCON
UCFG
USTAT
UADDR
UFRML
UFRMH
UIR
UIE
UEIR
UEIE
UEP0
UEP1
UEP2
UEP3
UEP4
UEP5
UEP6
UEP7
UEP8
UEP9
UEP10
UEP11
UEP12
UEP13
UEP14
UEP15
Legend:
Note 1:
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
49
OSCFIP
—
USBIP
—
—
HLVDIP
—
—
51
OSCFIF
—
USBIF
—
—
HLVDIF
—
—
51
OSCFIE
—
USBIE
—
—
HLVDIE
—
—
51
—
PPBRST
SE0
PKTDIS USBEN RESUME SUSPND
—
52
UTEYE UOEMON
—
UPUEN UTRDIS
FSEN
PPB1
PPB0
52
—
ENDP3
ENDP2
ENDP1
ENDP0
DIR
PPBI
—
52
—
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
52
FRM7
FRM6
FRM5
FRM4
FRM3
FRM2
FRM1
FRM0
52
—
—
—
—
—
FRM10
FRM9
FRM8
52
—
SOFIF STALLIF IDLEIF
TRNIF
ACTVIF UERRIF URSTIF
52
—
SOFIE STALLIE IDLEIE
TRNIE
ACTVIE UERRIE URSTIE
52
BTSEF
—
—
BTOEF DFN8EF CRC16EF CRC5EF PIDEF
52
BTSEE
—
—
BTOEE DFN8EE CRC16EE CRC5EE PIDEE
52
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
52
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
52
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
52
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
52
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
52
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
52
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
52
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
52
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
52
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
51
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
51
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
51
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
51
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
51
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
51
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
51
— = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 14-5.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 149