PIC18F2450 Datasheet, PDF (184/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
16.8 Use of the CCP1 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 counter will be reset to
zero. Timer1 is reset to automatically repeat the A/D
acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module but will still reset the Timer1 counter.
TABLE 16-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
49
PIR1
—
ADIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF
51
PIE1
—
ADIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE 51
IPR1
—
ADIP
RCIP
TXIP
—
CCP1IP TMR2IP TMR1IP 51
PIR2
OSCFIF
—
USBIF
—
—
HLVDIF
—
—
51
PIE2
OSCFIE
—
USBIE
—
—
HLVDIE
—
—
51
IPR2
OSCFIP
—
USBIP
—
—
HLVDIP
—
—
51
ADRESH A/D Result Register High Byte
50
ADRESL A/D Result Register Low Byte
50
ADCON0
—
—
CHS3
CHS2
CHS1 CHS0 GO/DONE ADON
50
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
50
ADCON2 ADFM
—
ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
50
PORTA
—
RA6⁽²⁾
RA5
RA4
RA3
RA2
RA1
RA0
51
TRISA
—
TRISA6⁽²⁾ TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
51
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
51
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
51
LATB
PORTE
TRISE⁽⁴⁾
LATE⁽⁴⁾
LATB7
—
—
—
LATB6
—
—
—
LATB5
—
—
—
LATB4 LATB3 LATB2 LATB1 LATB0
51
—
RE3^(1,3) RE2⁽⁴⁾
RE1⁽⁴⁾
RE0⁽⁴⁾
51
—
—
TRISE2⁽⁴⁾ TRISE1⁽⁴⁾ TRISE0⁽⁴⁾ 51
—
—
LATE2⁽⁴⁾ LATE1⁽⁴⁾ LATE0⁽⁴⁾
51
Legend:
Note 1:
2:
3:
4:
— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
These registers and/or bits are not implemented on 28-pin devices.
DS39760A-page 182
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© 2006 Microchip Technology Inc.