PIC18F2450 Datasheet, PDF (208/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
18.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro^® devices.
The user program memory is divided into three blocks.
One of these is a boot block of 1 or 2 Kbytes. The
remainder of the memory is divided into two blocks on
binary boundaries.
Each of the three blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 18-5 shows the program memory organization
for 24 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 18-3.
FIGURE 18-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2450/4450
MEMORY SIZE/DEVICE
16 Kbytes
(PIC18F2450/4450)
Boot Block
Block 0
Block 1
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
Address
Range
000000h
0007FFh
000FFFh
001000h
001FFFh
002000h
003FFFh
Block Code Protection
Controlled By:
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 18-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
300008h CONFIG5L —
—
—
—
—
300009h CONFIG5H —
CPB
—
—
—
30000Ah CONFIG6L —
—
—
—
—
30000Bh CONFIG6H —
WRTB WRTC
—
—
30000Ch CONFIG7L —
—
—
—
—
30000Dh CONFIG7H —
EBTRB
—
—
—
Legend: Shaded cells are unimplemented.
Bit 2
—
—
—
—
—
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
DS39760A-page 206
Advance Information
© 2006 Microchip Technology Inc.