PIC18F2450 Datasheet, PDF (173/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
15.4 EUSART Synchronous
Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any low-power
mode.
15.4.1 EUSART SYNCHRONOUS
SLAVE TRANSMIT
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREG register and then
the SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e) If enable bit TXIE is set, the interrupt will wake the
chip from Sleep. If the global interrupt is enabled,
the program will branch to the interrupt vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 15-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
49
PIR1
—
ADIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF
51
PIE1
—
ADIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE
51
IPR1
—
ADIP
RCIP
TXIP
—
CCP1IP TMR2IP TMR1IP
51
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
51
TXREG EUSART Transmit Register
50
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
51
BAUDCON ABDOVF RCIDL
—
SCKP BRG16
—
WUE ABDEN
51
SPBRGH EUSART Baud Rate Generator Register High Byte
50
SPBRG EUSART Baud Rate Generator Register Low Byte
50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 171