PIC18F2450 Datasheet, PDF (114/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
10.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected by clearing the T0CS bit
(T0CON<5>). In Timer mode, the module increments
on every clock by default unless a different prescaler
value is selected (see Section 10.3 “Prescaler”). If
the TMR0 register is written to, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In Counter mode, Timer0 increments either on
every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the Timer0 Source
Edge Select bit, T0SE (T0CON<4>); clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
10.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-Bit
mode; it is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor
writable (refer to Figure 10-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
FIGURE 10-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
T0CKI pin
T0SE
T0CS
T0PS2:T0PS0
PSA
1
Programmable ₀
Prescaler
3
Sync with
Internal
Clocks
(2 TCY Delay)
TMR0L
8
8
Set
TMR0IF
on Overflow
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-Bit mode with clock input from T0CKI maximum prescale.
FIGURE 10-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4
0
1
T0CKI pin
T0SE
T0CS
T0PS2:T0PS0
PSA
1
Programmable ₀
Prescaler
3
Sync with
Internal
Clocks
(2 TCY Delay)
TMR0L
8
TMR0
High Byte
8
Set
TMR0IF
on Overflow
8
TMR0H
Read TMR0L
Write TMR0L
8
Note: Upon Reset, Timer0 is enabled in 8-Bit mode with clock input from T0CKI maximum prescale.
8
Internal Data Bus
DS39760A-page 112
Advance Information
© 2006 Microchip Technology Inc.