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PIC18F2450 Datasheet, PDF (293/320 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology | |||
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PIC18F2450/4450
TABLE 21-17: A/D CONVERTER CHARACTERISTICS: PIC18F2450/4450 (INDUSTRIAL)
PIC18LF2450/4450 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
A01 NR
Resolution
â
â
10
bit ÎVREF ⥠3.0V
A03 EIL
Integral Linearity Error
â
â
<±1
LSb ÎVREF ⥠3.0V
A04 EDL Differential Linearity Error
â
â
<±1
LSb ÎVREF ⥠3.0V
A06 EOFF Offset Error
â
â
<±1.5
LSb ÎVREF ⥠3.0V
A07 EGN
A10 â
Gain Error
Monotonicity
â
â
<±1
Guaranteed(1)
LSb ÎVREF ⥠3.0V
â VSS ⤠VAIN ⤠VREF
A20 ÎVREF Reference Voltage Range
(VREFH â VREFL)
1.8
â
3
â
â
V VDD < 3.0V
â
V VDD ⥠3.0V
A21 VREFH Reference Voltage High
VSS
â
VREFH
V
A22 VREFL Reference Voltage Low
VSS â 0.3V â VDD â 3.0V V
A25 VAIN Analog Input Voltage
VREFL
â
VREFH
V
A30 ZAIN Recommended Impedance of
â
â
2.5
kΩ
Analog Voltage Source
A50 IREF VREF Input Current(2)
â
â
5
μA During VAIN acquisition.
â
â
150
μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
FIGURE 21-14: A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132
A/D DATA
9
8 7 ... ... 2
1
0
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
NEW_DATA
TCY(1)
DONE
Note 1:
2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 291
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