MAX11410 Datasheet, PDF (85/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Status_IE (0x39)
The STATUS_IE Register enables or disables status events from appearing as a logic OR of the INT signal state. For
every status register bit, there is a corresponding STATUS_IE bit. This register allows the INT signal to be used as a
system interrupt for any or all system status sources. Writing a 1 to a bit causes the corresponding STATUS bit state to
assert an interrupt. The specific cause of the interrupt can be discerned by reading the STATUS register. An interrupt can
be masked by disabling its corresponding enable bit in this register.
The default value of this register is 0x000001, enabling only CONV_RDY by default.
BIT
Field
Reset
Access Type
23
TOR_IE_7
Write, Read
22
TOR_IE_6
Write, Read
21
TOR_IE_5
Write, Read
20
TOR_IE_4
Write, Read
19
TOR_IE_3
Write, Read
18
TOR_IE_2
Write, Read
17
TOR_IE_1
Write, Read
16
TOR_IE_0
Write, Read
Bit
Field
Reset
Access Type
15
TUR_IE_7
Write, Read
14
TUR_IE_6
13
TUR_IE_5
12
TUR_IE_4
11
TUR_IE_3
10
TUR_IE_2
Write, Read Write, Read Write, Read Write, Read Write, Read
9
TUR_IE_1
Read Only
8
TUR_IE_0
Write, Read
Bit
Field
Reset
Access Type
7
SYSGOR_
IE
Write, Read
BITFIELD
TOR_IE_7
BITS
23
TOR_IE_6
22
TOR_IE_5
21
TOR_IE_4
20
TOR_IE_3
19
TOR_IE_2
18
TOR_IE_1
17
TOR_IE_0
16
TUR_IE_7
15
6
5
4
3
2
1
0
—
—
DATA_
RDY_IE
WAIT_ CAL_RDY_ SEQ_RDY_
DONE_IE
IE
IE
CONV_
RDY_IE
—
—
—
—
Write, Read Write, Read Write, Read Write, Read Write, Read
DESCRIPTION
DECODE
0: TOR_7 does not affect INT state.
1: INT asserts when TOR_7 = 1.
0: TOR_6 does not affect INT state.
1: INT asserts when TOR_6 = 1.
0: TOR_5 does not affect INT state.
1: INT asserts when TOR_5 = 1.
0: TOR_4 does not affect INT state.
1: INT asserts when TOR_4 = 1.
0: TOR_3 does not affect INT state.
1: INT asserts when TOR_0 = 1.
0: TOR_2 does not affect INT state.
1: INT asserts when TOR_2 = 1.
0: TOR_1 does not affect INT state.
1: INT asserts when TOR_1 = 1.
0: TOR_0 does not affect INT state.
1: INT asserts when TOR_0 = 1.
0: TUR_7 does not affect INT state.
1: INT asserts when TUR_7 = 1.
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