MAX11410 Datasheet, PDF (33/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Table 9a. LINEF = 00 Data Rate and Filter Rejection Settings
RATE
VALUE
0000
0001
0010
0011
0100-1111
FILTER TYPE
FIR50/60
FIR50/60
FIR50/60
FIR50/60
FIR50/60
REJECTION
(HZ)
50/60Hz
50/60Hz
50/60Hz
50/60Hz
50/60Hz
Single Cycle
1.0
2.0
4.0
8.0
16.0
DATA RATE (SPS)
Continuous
1.1
2.1
4.2
8.4
16.8
Table 9b. LINEF = 01 Data Rate and Filter Rejection Settings
RATE
VALUE
0000
0001
0010
0011
0100
0101-1111
FILTER TYPE
FIR50
FIR50
FIR50
FIR50
FIR50
FIR50
REJECTION
(HZ)
50Hz
50Hz
50Hz
50Hz
50Hz
50Hz
Single Cycle
1.3
2.5
5.0
10.0
20.0
35.6
DATA RATE (SPS)
Continuous
1.3
2.7
5.3
10.7
21.3
40
Table 9c. LINEF = 10 Data Rate and Filter Rejection Settings
RATE
VALUE
0000
0001
0010
0011
0100
0101-1111
FILTER TYPE
FIR60
FIR60
FIR60
FIR60
FIR60
FIR60
REJECTION
(HZ)
60Hz
60Hz
60Hz
60Hz
60Hz
60Hz
Single Cycle
1.3
2.5
5.0
10.0
20
35.6
DATA RATE (SPS)
Continuous
1.3
2.7
5.3
10.7
21.3
40
Table 9d. LINEF = 11 Data Rate and Filter Rejection Settings
RATE
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
FILTER TYPE
SINC4
SINC4
SINC4
SINC4
SINC4
SINC4
SINC4
SINC4
SINC4
SINC4
REJECTION
(HZ)
4
10
20
40
60
120
240
480
960
1920
Single Cycle
1
2.5
5
10
15
30
60
120
240
480
DATA RATE (SPS)
Continuous
4
10
20
40
60
120
240
480
960
1920
Duty Cycle
0.3
0.5
1.1
2.1
4.2
Duty Cycle
0.3
0.7
1.3
2.7
5.3
10.0
Duty Cycle
0.3
0.7
1.3
2.7
5.3
10.0
Duty Cycle
1
2.5
5
10
15
30
60
120
240
480
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