MAX11410 Datasheet, PDF (84/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
BITFIELD
TUR_0
BITS
8
SYSGOR
7
WAIT_DONE
3
CAL_RDY
2
SEQ_RDY
1
CONV_RDY
0
DESCRIPTION
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
DECODE
0: Normal operation
1: Threshold underrange/digital underrange condition on
channel 0. Clears when the STATUS register is read.
0: No fault detected
1: A system gain calibration was overrange. Clears when
the STATUS register is read.
0: No change
1: Wait operation has completed. Clears on a read of the
STATUS register or a write to the WAIT_START register
0: No change
1: Calibration complete. New calibration result(s) Available in
the SYS or SELF calibration registers. Clears on a read
of the STATUS register or a write to the CAL_START
register.
0: No sequence completed, or status bit has been reset.
1: Sequence has completed at least one iteration.
Cleared by a read of the status register, a write to the
SEQ_START register (including within a sequence), or a
sequence wraparound from µC52->µC0.
0: Normal operation
1: New conversion result(s) available in the DATA
registers. Cleared by a read of the STATUS register, a
write to the CONV_START register, or just prior to the
availability of a new conversion result in continuous or
duty cycle mode.
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