MAX11410 Datasheet, PDF (38/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Register Address Byte
Write to this register (shown in clock cycles 0 through 7 in the SPI Timing Diagram) to begin any read or write transaction.
The R/WB bit selects whether the transaction is a read or write. The REG_ADDR bits select the address of the register
to be written or read. There are three register maps, with register widths of 8, 16, and 24 bits. Because register sizes are
variable, the REG_ADDR bits also determine the length of the transaction.
REGISTER
ADDRESS
R/W
SIZE
(BITS)
DEFAULT
VALUE
D7
D6
D5
D4
D3
D2
D1
D0
ADDR
XX
W
8
—
R/WB
REG_ADDR[6:0]
FIELD NAME
—
R/WB
BIT(S)
7:2
7
REG_ADDR[6:0]
6:0
DEFAULT
—
—
—
R/WB
0
1
REG_ADDR[6:0]
FUNCTION
—
DESCRIPTION
Write to the register at address REG_ADDR[6:0].
Read the register at address REG_ADDR[6:0].
DESCRIPTION
Read or write (based the value of R/WB) the register at
this address.
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