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MAX11410 Datasheet, PDF (42/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power
MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
GP0_CTRL (0x04)
The GP0_CTRL register controls the behavior of GPIO0. Writes of reserved values are ignored. The GPIO_0 Direction
Select field (GP0_DIR) selects whether GPIO_0 will behave as an input or an output. Open-drain or CMOS output
MAX11410 may be selected. The GPI0_0 Input Select field (GP0_INSEL) selects the operation of the GPIO_0 pin when
configured as an input using the GP0_DIR field.
The GPIO Output Select field, GP0_OSEL, controls the output operation of the GPIO_0 pin when configured as an output
using the GP0_DIR field. When the GPIO is set for rising-edge-triggered conversion start or rising-edge-triggered
sequencer start, if in PD: SLEEP or PD: STANDBY mode, the rising edge changes the mode to PD: normal mode and
then initiates the conversion or sequence. The minimum pulse width for a GPIO input is 2 x tCLK.
BIT
Field
Reset
Access Type
7
6
GP0_DIR[1:0]
Write, Read
5
4
3
2
1
0
GP0_ISEL[1:0]
—
GP0_OSEL[2:0]
—
Write, Read
—
Write, Read
BITFIELD
BITS
GP0_DIR
7:6
GP0_ISEL
5:4
GP0_OSEL
2:0
DESCRIPTION
DECODE
00: Input mode, reference to VDDIO (default)
01: Reserved
10: Output mode, open-drain output
11: Output mode, CMOS output
00: GPIO_0 input disabled (default)
01: GPIO_0 input configured as rising-edge-triggered
conversion start
10: GPIO_0 input configured as rising-edge-triggered
conversion start
11: Reserved
000: GPIO_0 output disabled, high Z (default)
001: GPIO_0 output is configured as INTRB (active low)
010: GPIO_0 output is configured as INTR (active high)
011: GPIO_0 output is configured as state Logic 0
100: GPIO_0 output is configured as state Logic 1
101: GPIO_0 output is configured as automatic low-side
switch operation (CMOS output mode overridden)
110: GPIO_0 output is configured as modulator active
status
111: GPIO_0 output is configured as system clock
(2.456Mhz Nominal)
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