MAX11410 Datasheet, PDF (20/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Pin Description (continued)
PIN
MAX11410
10
NAME
AIN7
FUNCTION
Channel 7 Input. May serve as either the positive or negative
differential input. May also serve as current source output.
REF SUPPLY
TYPE
AV_DD
Analog Input
11
AIN8
Channel 8 Input. May serve as either the positive or negative
differential input. May also serve as current source output.
AV_DD
Analog Input
12
AIN9
Channel 9 Input. May serve as either the positive or negative
differential input. May also serve as current source output.
AV_DD
Analog Input
13
AGND
Analog Ground Voltage for AV_DD Supply. Connect AGND and GND
together.
N/A
Ground
14
AVDD
Analog Supply Voltage, +2.7V to +3.6V with respect to AGND.
AV_DD
Power
This pin serves a dual function. Serial Data Output: the device will
drive this pin in response to a serial clock at SCLK, when data is
15
DOUT/INTB
read from the internal registers. In addition to the serial data output
function, the DOUT/INTB pin also indicates an enabled interrupt
V_DDIO
Digital Output
condition has occurred when the pin is asserted low. To view the
interrupt state on DOUT/INTB, enable CSB.
16
GPIO1 Register-Controlled, General-Purpose Input/Output.
AV_DD
Digital I/O
Serial Data Input. Data present at DIN is shifted in to the part’s internal
17
DIN
registers in response to a serial clock at SCLK, either when the part is
V_DDIO
Digital Input
accessed for an internal register write or for a command operation.
Chip Select Bar. Active-Low Logic Input. Use CSB to select the IC
18
CSB
for access through the serial interface. CSB is used for frame
synchronization for communications when SCLK is continuous. CSB
V_DDIO
Digital Input
transitioning from low to high is used to reset the SPI interface.
19
SCLK
Serial Clock. Logic Input. Apply an external serial clock to this input
to issue commands to or access data.
V_DDIO
Digital Input
20
VDDREG Digital Regulator Supply, Connect to AVDD.
AV_DD
Power
Register Controlled General Purpose Input/Output and External
Clock Signal Input. When external clock mode is selected (EXTCLK
21
GPIO0 = 1), provide a 2.4576MHz clock signal at CLK. Other frequencies
AV_DD
Digital I/O
can be used, but the data rate and digital filter notch frequencies
scale accordingly.
22
CAPREG
Digital Regulator Output. Connect a 100nF capacitor from
CAPREG to AGND.
AV_DD
Power
23
VDDIO Digital Interface Supply (+1.8V to +3.6V).
24
GND
Ground Reference for V_DDIO. Connect to AGND.
25
REF2P
Positive Differential Reference 2 Input. REF2P must be more
positive than REF2N.
V_DDIO
N/A
AV_DD
Power
Ground
Analog Input
26
REF2N
Negative Differential Reference 2 Input. REF2P must be more
positive than REF2N.
AV_DD
Analog Input
27
REF1P
Positive Differential Reference 1 input. REF1P must be more
positive than REF1N.
AV_DD
Analog Input
28
REF1N
Negative Differential Reference 1 input. REF1P must be more
positive than REF1N.
AV_DD
Analog Input
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