MAX11410 Datasheet, PDF (14/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
Electrical Characteristics (continued)
(AV_DD = +3.3V, V_DDIO = +1.8V, V_REFP - V_REFN = AV_DD, T_A = T_MIN to T_MAX, unless otherwise noted., T_A=+25°C for typical specifica-
tions, unless otherwise noted, Note 1 )
PARAMETER
SYMBOL
CONDITIONS
MIN
CSB Fall to SCLK Fall
Setup Time
t_CSS0
CSB falling edge to the 1st SCLK falling
edge
40
CSB Rise to SCLK Fall
Hold Time
t_CSH1
Applies to the last active SCLK falling edge
3
CSB Rise to SCLK Fall
t_CSA
Applies to last active SCLK falling edge,
aborted sequence
12
CSB Pulse-Width High
SCLK Fall to CS Fall
DIN to SCLK Rise Setup
Time
t_CSPW
t_CSF
t_DS
40
Applies to the last active SCLK falling edge 100
40
DIN to SCLK Rise Hold
Time
t_DH
2
DOUT Propagation
Delay
t_DOT
Delay from the falling clock edge to the
transition on DOUT
DOUT Enable Time
t_DOE
0
DOUT Disable Time
t_DOZ
Bus Capacitance
C_B
LOGIC INPUTS AND OUTPUTS (NON-GPIO)
Input Current
Leakage current
Input Low Voltage
Input High Voltage
Input Hysteresis
Input Capacitance
V_IL
V_IH
V_HYS
0.7 x
V_DDIO
Output Low Level
Output High Level
High-Z Leakage Current
High-Z Output
Capacitance
V_OL
V_OH
I_OL = 1mA, V_DDIO = 1.8V and 3.6V
I_OL = 1mA, V_DDIO = 1.8V and 3.6V
Note 2
0.9 x
V_DDIO
-100
TYP
200
5
9
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
40
ns
40
ns
25
ns
20
pF
±1
uA
0.3 x
V_DDIO
V
V
mV
pF
0.1 x
V_DDIO
V
V
+100
nA
pF
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