MAX11410 Datasheet, PDF (51/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
PGA (0x0E)
The PGA register controls the signal path by enabling or disabling the input buffers and the PGA, and by setting the
gain. The Signal Path Select field (SIG_PATH) selects whether the multiplexer output will be connected to the modulator
directly, through the low-power buffer, or through the PGA. The GAIN field selects the analog gain setting for the PGA.
When When the input signal buffer or direct signal path is selected, this field selects the digital gain setting. When
configured for digital gain (PGA disabled) any gain setting higher than 4x will default to 4x.
BIT
7
6
5
4
3
2
1
0
Field
—
—
SIG_PATH[1:0]
—
GAIN[2:0]
Reset
—
—
—
Access Type
—
—
Write, Read
—
Write, Read
BITFIELD
BITS
SIG_PATH
5:4
GAIN
2:0
DESCRIPTION
DECODE
00: Buffered, low-power, unity-gain path
(PGA disabled, digital gain) [default]
01: Bypass path (signal buffer disabled,PGA disabled,
digital gain)
10: PGA path (signal buffer disabled, analog gain)
11: Reserved
000: 1 (default)
001: 2
010: 4
011: 8
100: 16
101: 32
110: 64
111: 128
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