MAX11410 Datasheet, PDF (45/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
FILTER (0x08)
The Filter register selects both the conversion data rate and the behavior of the digital filter. The LINEF field selects one
of four digital filter options. The RATE field select the data rate. The options available for the RATE field are determined
by the LINEF selection. See the tables in the Digital Gain section for details.
BIT
7
6
5
4
3
2
1
0
Field
—
RESERVED
(0)
LINEF[1:0]
RATE[3:0]
Reset
—
Access Type
—
Write, Read
Write, Read
Write, Read
BITFIELD
RESERVED
(0)
LINEF
RATE
BITS
6
5:4
3:0
DESCRIPTION
Reserved; always set to 0.
DECODE
0: Always set to 0.
Sets filter type.
00: Simultaneous 50/60Hz FIR rejection (default)
01: 50Hz FIR rejection
10: 60Hz FIR rejection
11: SINC4
Sets conversion rate based on LINEF value.
See Table 9a through Table 9d for details.
CTRL (0x09)
The CTRL register selects the clock source, the unipolar/bipolar data format, the reference inputs, and the reference
buffers.
The External Clock Enable (EXTCLK) bit selects the whether the system clock source will be internal or external. Setting
EXTCLK to '1' will override any settings in the GP0_CTRL register. A write to the EXTCLK bit inside of a sequence will be
ignored. Changing clock sources inside of a sequence is not supported; a write to the EXTCLK bit inside of a sequence
will be ignored.
The Unipolar/Bipolar Select (U_BN) bit selects whether the input range is bipolar or unipolar. A ‘1’ in this bit location
selects unipolar input range and a ‘0’ selects bipolar input range. The Format Select (FORMAT) bit controls the data
format when in bipolar mode (U_BN = 0). Unipolar data is always in straight binary format. The FORMAT bit has no effect
in Unipolar mode (U_BN = 1). In bipolar mode, if the FORMAT bit = 1, then the data format is offset binary. If the FORMAT
bit = 0, then the data format is two’s complement. (See Table 6.)
Writing to the FORMAT or U_BN bits does not change the values programmed in any threshold registers. However, it
will affect the interpretation of these registers. When updating the FORMAT or U_BN bits, threshold registers should
be re-written with values that agree with the new format. Any input exceeding the available input range is limited to the
minimum or maximum data value.
The Reference P-Side and N-Side Buffer Enable bits (REFBUFP and REFBUFN) control whether the reference input
buffers will be enabled.
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