MAX11410 Datasheet, PDF (81/95 Pages) Maxim Integrated Products – 24-Bit Multi-Channel Low-Power

MAX11410
24-Bit Multi-Channel Low-Power
1.9ksps Delta-Sigma ADC with PGA
DATA7 (0x37)
The ADC conversion result is stored in DATA7 if this register is selected by the state of the DEST or GP_DEST register.
BIT
23
22
21
20
19
18
17
16
Field
DATA7[23:16]
Reset
Access Type
Write, Read
Bit
15
14
13
12
11
10
9
8
Field
DATA7[15:8]
Reset
Access Type
Write, Read
Bit
7
6
5
4
3
2
1
0
Field
DATA7[7:0]
Reset
Access Type
Write, Read
BITFIELD
DATA7
BITS
23:0
Conversion data.
DESCRIPTION
Status (0x38)
The STATUS register can be read to determine the state
of the device and determine the cause of INTB signal
assertion. Most STATUS register bits are cleared by a
STATUS Register Read.
The TOR bits are Threshold Register Over-Range Status
bits. When one is set, it indicates that the corresponding
DATA register value is greater than the value set by the
UTHRESH register or the ADC conversion result has
created a digital under-range condition. TOR will clear
when the STATUS register is read. TOR register bits do
not self-clear.
The TUR bits are Threshold Register Under-Range
Status bits. When one is set, it indicates that the
corresponding DATA register value is less than the value
set by the LTHRESH register or the ADC conversion
result has created a digital underrange condition. TUR will
clear when the STATUS register is read. TUR register bits
do not self-clear.
The System Gain Over-Range Status bit (SYSGOR)
indicates that a system gain calibration was overrange.
The SYS_GAIN calibration coefficient has a maximum
value of 1.9999999 (0xFFFFFF). When set to ‘1’, SYSGOR
indicates that full-scale value out of the converter is likely
not available. SYS_GOR will clear when the STATUS
register is read, or if a new System Gain calibration yeilds
a valid result.
The DATA_RDY bit indicates that the DATA registers contain
unread ADC conversion results. This bit is cleared when
all unread DATA registers have been read. Unlike other
status bits, DATA_RDY is not cleared by a STATUS
register read. The DATA_RDY status bit is a logical OR of
8 internal register status bits that are set when new ADC
data is written to a DATA register, and are cleared when
the corresponding DATA register is read.
Example 1: A CONV_START is performed with 0x70 as
the operand. The ADC completes the single conversion.
DATA7 contains new conversion data and DATA_RDY is
set. Next, the contents of the DATA7 register are read.
This causes the corresponding internal register to clear,
and the DATA_RDY status bit is cleared.
Example 2: A CONV_START is performed with 0x61 as
the operand. The ADC is in a continuous-conversion
mode, writing to the DATA6 register and setting the
DATA_RDY status bit. The DATA_RDY bit remains set
until the DATA6 register has been read. As the ADC is
continuously converting, the DATA_RDY bit will be set
again as new data is written to the DATA6 register.
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